As shown in this figure, in such a conventional demodulator, the received high frequency signal is initially amplified by an automatic gain control circuit 10 for regulating its level. The amplified received signal is then split into two identical signals by a coupler 12.
The output signal from a non-synchronized local oscillator 14 whose nominal frequency is close to that of the received signal is applied in parallel both to a cell 16 having a first output 17 on which it delivers an in-phase oscillator signal and a second output 18 on which it delivers a quadrature oscillator signal which is phase shifted by 90.degree..
One of the two signals from the coupler 12 is transposed into in-phase baseband by being multiplied in a mixer 20 with the in-phase oscillator signal from the output 17 of the cell 16. The other signal from the coupler 12 is transposed into quadrature baseband in a mixer 30 by being multiplied with the quadrature oscillator signal from the output 18 of the cell 16.
The signals from the mixers 20 and 30 are applied to respective lowpass filters 22 and 32. In this way, the outputs of the two filters 22 and 32 provide two components, namely an in-phase component and a quadrature component, representative of the received signal. These components are applied to respective amplifiers 24 and 34 and then to respective analog-to-digital converters 26 and 36. Thus, the outputs of the analog-to-digital converters 26 and 36 provide respective samples Y.sub.p,k and Y.sub.q,k (where p designates in-phase component samples, q designates quadrature component samples, and k designates sample rank or number).
Synchronizing and decision-making functions are then performed by digital processing specific to the type of modulation used and performed in a unit given general reference 40 in FIG. 1.
The Applicants have observed that the analog portion of the demodulator, prior to the digital processing suffers from several faults:
level regulation is not perfect, thereby causing sample level to vary as a function of fluctuations in the received signal; PA1 the two channels may be unbalanced in amplitude due to different gains; PA1 the rest voltages of the channels may be offset in the amplifiers 24, 34, and/or in the analog-to-digital converters 26, 36; and PA1 the two demodulated channels may not be exactly in quadrature with each other.
These faults also depend on operating frequency and on temperature. They are therefore difficult to compensate using known techniques. They degrade demodulator performance (i.e. they increase the binary error rate).
The performance of a digital link is generally evaluated from the curve of bit error rate (TEB) as a function of the ratio Eb/No (where Eb=the energy expended for transmitting one bit, and No=the noise power density on the link).
The existence of demodulator faults gives rise to a need to increase the ratio Eb/No by a quantity .delta.(Eb/No) in order to obtain the same error rate as would be obtained if there were no faults. The following examples are intended to illustrate this phenomenon.
With BPSK (binary phase shift keying) having voltage offsets on one channel, or with QPSK (quaternary phase shift keying) with identical offsets on both channels, the ratio Eb/No at low error rates (TEB&lt;10.sup.-6) is degraded as follows:
.delta.(Eb/No)=0.3 dB for an offset of 5% of the useful signal; and
.delta.(Eb/No)=0.7 dB for an offset of 10% of the useful signal.
With QPSK and a quadrature error .delta..theta. between the two channels, the resulting degradation can be considered as being due to an error in carrier recovery equal to 1/2.delta..theta., giving: EQU .delta.(Eb/No)=0.4 dB for .delta..theta.=5.degree.; and EQU .delta.(Eb/No)=0.8 dB for .delta..theta.=10.degree..
The object of the present invention is to propose a circuit for dynamically estimating and correcting in digital manner the above-described faults in the analog portion of the modulator, without requiring a test signal and without disturbing the link in operation, thereby improving transmission performance.